Why does mulss take only 3 cycles on Haswell, different from Agner's instruction tables? (Unrolling FP loops with multiple accumulators)

c#assemblyx86micro-optimizationsse
Show Solution

Can x86's MOV really be "free"? Why can't I reproduce this at all?

c#cpu-architectureassemblyx86micro-optimization
Show Solution

What considerations go into predicting latency for operations on modern superscalar processors and how can I calculate them by hand?

performancecpu-architectureassemblyx86-64latency
Show Solution

How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent

cpu-architectureassemblyx86micro-optimizationintel
Show Solution

Test whether a register is zero with CMP reg,0 vs OR reg,reg?

optimizationassemblyx86micro-optimization
Show Solution

More Tags

opengl-esdistancegradle-eclipsec++11latencyjavascript-namespacesevent-bubblingoperator-precedenceiframefile-accessandroid-dialogangular2-templaterelative-importdata-sharingjquery-validatecapitalizationoption-stricteditorconfigurationvertical-alignment