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Why is processing a sorted array faster than processing an unsorted array?
java
c++
performance
cpu-architecture
branch-prediction
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Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?
performance
cpu-architecture
assembly
x86
intel
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Micro fusion and addressing modes
cpu-architecture
assembly
x86
intel
iaca
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Why doesn't GCC use partial registers?
cpu-architecture
gcc
assembly
x86-64
x86
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Can x86's MOV really be "free"? Why can't I reproduce this at all?
c#
cpu-architecture
assembly
x86
micro-optimization
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